Analysis and Design Considerations for High Performance Caches

Memory access is the major bottleneck of today's high-performance microprocessors. This thesis provides a systematic and quantitative analysis of the performance trade-offs of major cache (fast memory) topologies. It allows early insight into these trade-offs because performance and costs are controlled by circuit and layout level issues which are difficult to evaluate at initial stages in a design. The thesis establishes a common reference frame that incorporates many implementation possibilities. Within this frame, objective comparisons are made to observe the behavior of caches of various sizes and bandwidths. The approach was to first optimize the speed of a building block, and then to use the block consistently to design larger cache circuits, such as 16Kbyte and 32Kbyte single-ported, and 8Kbyte and 16Kbyte dual-ported to achieve different optimization goals. The simulation results of the circuits are collected in the R Spreadsheet. It presents the effectiveness of the design considerations for optimizing speed, bandwidth, and area (to reduce power consumption) to meet a variety of specifications. One result is that doubling the size of an 8Kbyte single-ported cache in the common reference frame increases the access time by less than 10%. The results are process-independent, allowing the spreadsheet to serve as a convenient reference for cache design and research. Thesis Supervisor: Thomas F. Knight JR Title: Senior Research Scientist